1. Field of the Invention
The present invention relates to a delay circuit and a ring oscillator using the same.
2. Description of the Related Art
In various applications, delay circuits that delay an input signal by a given time are used. In, for example, a MOST (Media Oriented Systems Transport) system that is a standard for vehicle-mounted networks, a digital signal to be transmitted and a clock signal are multiplexed (encoded) when transmitting the digital signal. The digital signal having the clock signal multiplexed therewith is transmitted to the destination apparatus, which extracts the original clock signal from the digital signal. In this extraction, a delay circuit is used.
FIG. 9 shows the configuration of a conventional clock extracting circuit for the differential-bi-phase-encoded digital signal (hereinafter called differential bi-phase code). (Refer to, for example, Japanese Patent Application Laid-Open Publication No. H11-136295.) FIG. 10 is a timing chart showing the operation of the conventional clock extracting circuit of FIG. 9.
First, the differential bi-phase code (see FIG. 10(b)) for digital data of a predetermined bit rate (see FIG. 10(a)) is transmitted to the conventional clock extracting circuit. An exclusive OR gate 16 performs an exclusive OR operation between the differential bi-phase code received and a delayed signal (see FIG. 10(c)) produced by a delay circuit 15 delaying the differential bi-phase code by a predetermined amount of time. The results of this operation are edge detection pulses (see FIG. 10(d)) indicating the rising edges and falling edges of the received differential bi-phase code being detected. An AND gate 17 performs an AND operation between the edge detection pulses and the output of a mono-multivibrator 18 (see FIG. 10(e)). The mono-multivibrator 18 generates a pulse of a predetermined width on the falling edge of a trigger signal (see FIG. 10(f)) that is the output of the AND gate 17.
The conventional clock extracting circuit performs the above series of operations and provides as a clock signal the output of the mono-multivibrator 18 based on the edge detection pulses from the received differential bi-phase code. In this way, the conventional clock extracting circuit uses delay circuits such as the delay circuit 15 and the mono-multivibrator 18 when extracting the clock signal.
Furthermore, for example, a ring oscillator circuit that generates an oscillation clock signal of a given frequency comprises inverter circuits that are delay circuits. FIG. 11 shows the configuration of a conventional ring oscillator circuit (refer to, for example, Japanese Patent Application Laid-Open Publication No. H08-186474).
The conventional ring oscillator circuit comprises a current control unit 20 and a ring oscillator unit 30.
In the current control unit 20, by a sum current (I1+I) of a current I1 from a constant current source and a control current i flowing through the drain of a transistor Q1, the sum current (I1+I) is copied into a transistor Q3. The current flowing through the transistor Q3 flows through a transistor Q2. The current flowing through the transistors Q2, Q3 is copied into drive transistors Q4a to Q4n and Q7a to Q7n to drive inverters 31a to 31n in the ring oscillator unit 30.
The ring oscillator unit 30 comprises the inverters 31a to 31n that have a delay time τ which are connected to be shaped like an n-stage ring. The inverters 31a to 31n have P-MOS transistors Q5a to Q5n and N-MOS transistors Q6a to Q6n respectively connected in series, and are supplied with a drive current i respectively via the drive transistors Q4a to Q4n on the source power (VCC) line side and the drive transistors Q7a to Q7n on the sink power (GND) line side. Pairs of the drive transistor Q4a to Q4n on the source power line side and the transistor Q2 each form a current mirror circuit, and pairs of the drive transistors Q7a to Q7n on the sink power line side and the transistor Q2 each form a current mirror circuit.
Where the drive currents i are flowing through the inverters 31a to 31n, when the input of the first stage inverter 31a is at a high (H) level, the last stage inverter 31n outputs a low (L) level with a delay time of n·τ. The output of the last stage inverter 31n is directly fed back to the input of the first stage inverter 31a. Hence, after another time of n·τ elapses, the output of the last stage inverter 31n becomes the H level. In this way, the output of the last stage inverter 31n repetitively takes on the H level/L level, generating an oscillation clock signal having an oscillation frequency f of 1/2n·τ.
With reference to FIG. 12, a usual voltage-current characteristic of a MOS transistor will be explained. As shown in FIG. 12, when the drain-to-source voltage VDS is low, the drain current ID linearly increases with the drain-to-source voltage VDS increasing, which is in a linear region. On the other hand, when the drain-to-source voltage VDS is high, the drain current ID is almost constant with the drain-to-source voltage VDS increasing, which is in a saturation region showing a constant-current characteristic.
As the operation range of a MOS transistor, the saturation region is mainly used where the drain current ID shows a constant-current characteristic. In the saturation region, the drain current ID increases with the gate-to-source voltage VGS increasing and decreases with the gate-to-source voltage VGS decreasing. In the saturation region, there is usually a relationship that the drain current ID is proportional to the gate-to-source voltage VGS squared as expressed by the equation (1):ID=β/2(VGS−VT)^2,   (1)where β and VT are a gain and threshold voltage of the MOS transistor.
With reference to FIG. 13, a characteristic of a usual current mirror circuit will be explained.
FIG. 13(a) shows the configuration of the usual current mirror circuit, and FIG. 13(b) shows the characteristic thereof. In FIG. 13(b), the vertical axis represents a copied current I2 copied from a current I1 of a constant current source, and the horizontal axis represents power supply potential VCC. The characteristics shown in FIG. 13(b) indicate how the copied current I2 changes with varying the power supply potential VCC and varying the current I1 of the constant current source by steps of 10 μA from 10 μA to 100 μA. Comparing FIGS. 12 and 13, power supply potential VCC corresponds to the drain-to-source voltage VDS of a MOS transistor T1 and the copied current I2 corresponds to the drain current ID of the MOS transistor T1.
As shown in FIG. 13(a), in the current mirror circuit, as a result of the current I1 of the constant current source driving the MOS transistor T2, the drain-to-source voltage VDS of the MOS transistor T2 is applied as the gate-to-source voltage VGS of the MOS transistor T1. Since the gate electrodes of the MOS transistors T1, T2 are connected in common, their gate-to-source voltages VGS are equal. With this configuration, the current I1 flowing through the MOS transistor T2 is copied as the current I2 that flows through the MOS transistor T1.
As shown in FIG. 13(b), when power supply potential VCC is low, the copied current I2 is located in the linear region with not showing a constant-current characteristic. On the other hand, when power supply potential VCC is high, the copied current I2 is located in the saturation region with showing a constant-current characteristic. Since in the saturation region the drain currents ID of the MOS transistors T1, T2 are both proportional to the gate-to-source voltage VGS squared (see the equation (1)), the copied current I2 and the current I1 of the constant current source are in a linear relationship.
Therefore, to make the copied current I2 linearly follow the current I1 of the constant current source, the operation range of the MOS transistor T1 need be set to be in the saturation region by setting power supply potential VCC or the drain-to-source voltage VDS of the MOS transistor T1 high.
In the inverters 31a to 31n of FIG. 11, the drive transistors Q4a to Q4n and the drive transistors Q7a to Q7n forming part of the current mirror circuits are respectively connected to the source power line side and the sink power line side of the inverters 31a to 31n. That is, each of the inverters 31a to 31n is configured to be driven by the two current mirror circuits provided on the source power line side and the sink power line side. The ring oscillator unit 30 is configured to have sets of the four transistors (Q4, Q5, Q6, Q7) connected in series between the source power line side and the sink power line side.
Hence, if the drive current i is increased, enough drain-to-source voltage VDS may not be developed across the transistors (Q4, Q5, Q6, Q7). In this case, the transistors (Q4, Q5, Q6, Q7) go outside the constant current operation range and the drive current i does not linearly follow the control current (I1+I). The swing of the output voltages of the inverters 31a to 31n varies causing the delay time τ to vary.
As such, conventional delay circuits such as the inverters 31a to 31n shown in FIG. 11 are configured to be driven respectively by current sources provided on the source power line side and the sink power line side (current mirror circuits or the like). With this configuration, capability to linearly follow the control signal (current/voltage) cannot be obtained and accuracy in setting the delay time may be degraded.